Micro-27 Final Program

Wednesday, November 30

9:00-10:00 Kenote Address: Wen-Mei Hwu, Illinois
Title: "VLIW: is it for real this time?" (779022 bytes)

10:30-12:00 Session 1: Branch Profiling and Classification
"Static Branch Frequency and Program Profile Analysis" , Youfeng Wu - Sequent Computer Systems, James R. Larus - Wisconsin (USA)
"Using Branch Handling Hardware to Support Profile-Driven Optimization" , Thomas M. Conte, Burzin A. Patel - South Carolina, J. Stan Cox - AT&T (USA)
"Branch Classification: A New Mechanism for Improving Branch Predictor Performance" , Po-Yung Chang, Yale Patt - University of Michigan, Ann Arbor (USA)

1:30-3:00 Session 2: Random Acts of Research
"Techniques for Compressing Program Address Traces", Andrew Pleszkun - University of Colorado, Boulder (USA)
"Height Reduction of Control Recurrences for ILP Processors", Michael Schlansker, Vinod Kathail, Sadun Anik - HP Labs (USA)
"Theoretical Modeling of Superscalar Processor Performance", Derek B. Noonburg, John P. Shen - Carnegie Mellon University (USA)

3:30-5:20 Session 3: Software Pipelining and ILP Scheduling
"Iterative Modulo Scheduling: An Algorithm For Software Pipelining Loops", B. Ramakrishna Rau - HP Labs (USA)
"Minimum Register Requirements for a Modulo Schedule", Alexandre E. Eichenberger, Edward S. Davidson - University of Michigan, Ann Arbor, Santosh G. Abraham - HP Labs (USA)
"Minimizing Register Requirements under Resource-Constrained Rate-Optimal Software Pipelining", R. Govindarajan - Newfoundland, Erik R. Altman, Guang R. Gao - McGill (CANADA)
"Software Pipelining with Register Allocation and Spilling", Jian Wang, Andreas Krall, M. Anton Ertl - Technische Universitat Wein (AUSTRIA), Christine Eisenbeis - INRIA (FRANCE)

Thursday, December 1

9:30-10:30 Session 4: Memory Disambiguation
"Reducing Memory Traffic with CRegs", Peter Dahl, Matthew O'Keefe - University of Minnesota (USA)
"Dynamic Memory Disambiguation for Array References", David Bernstein, Doron Cohen - IBM (ISRAEL), Dror E. Maydan - SGI (USA)
"A Study of Pointer Aliasing for Software Pipelining using Run-time Disambiguation", Bogong Su, Stanley Habib - CUNY, Wei Zhao - Case Western (USA), Jian Wang - Technische Universitat Wein (AUSTRIA), Youfeng Wu - Sequent (USA)

11:00-12:00 Session 5: Memory System Optimizations
"Data Relocation and Prefetching for Programs with Large Data Sets", Yoji Yamada, John Gyllenhaal, Grant Haab, Wen-mei Hwu - University of Illinois, Urbana (USA)
"Cache Designs with Partial Address Matching", Lishing Liu, IBM

1:30-3:00 Session 6: Hardware Evaluation and Analysis
"Minimizing Branch Misprediction Penalties for Superpipelined Processors", Ching-Long Su, Alvin M. Despain - USC (USA)
"Facilitating Superscalar Processing via a Combined Static/Dynamic Register Renaming Scheme", Eric Sprangle, Yale Patt - University of Michigan, Ann Arbor (USA)
"Improving Resource Utilization of the MIPS R8000 via Post-Scheduling Global Instruction Distribution", Raymond Lo, Sun Chan, Fred Chow, Shin-Ming Liu - MIPS Technologies (USA)
"A Comparison of Two Pipeline Organizations", Michael Golden, Trevor Mudge - University of Michigan, Ann Arbor (USA)

3:30-5:20 Session 7: Hardware Design
"A Fill-Unit Approach to Multiple Instruction Issue", Manoj Franklin, Mark Smotherman - Clemson University (USA)
"A High-Performance Microarchitecture with Hardware-Programmable Functional Units", Rahul Razdan - DEC (USA), Michael D. Smith - Harvard University (USA)
"The Anatomy of the Register File in a Multiscalar Processor", Scott E. Breach, T. N. Vijaykumar, Gurindar S. Sohi - Wisconsin (USA)
"Register File Port Requirements of Transport Triggered Architectures", Jan Hoogerbrugge, Henk Corporaal - Delft University (NETHERLANDS)

6:30-9:00 Conference Dinner
Invited Speaker: Steve Wallach, Convex
Title:"Toward a TeraMips future"

Friday, December 2nd

9:00-10:00 Invited Speaker: Kunle Olukotun, Stanford
Title:"Multiprocessor Microarchitectures: A New Direction for High Performance Computing"

10:30-12:20 Session 8: Predicated Execution and Branch Prediction
"The Effects of Predicated Execution on Branch Prediction", Gary Tyson - University of California, Davis (USA)
"Analysis of the Conditional Skip Instructions of the HP Precision Architecture", Jonathan P. Vogel - Telxon Corporation (USA), Bruce K. Holmer - Northwestern University (USA)
"Characterizing the Impact of Predicated Execution on Branch Prediction", Scott A. Mahlke, Richard E. Hank, Roger A. Bringmann, John C. Gyllenhaal, David M. Gallagher, Wen-mei W. Hwu - University if Illinois, Urbana (USA)
"The Effect of Speculatively Updating Branch History on Branch Prediction Accuracy, Revisited", Eric Hao, Yale Patt - University of Michigan, Ann Arbor (USA)

12:20-1:45 Conference Luncheon
1:45-3:00 Invited Speaker: Leslie Kohn, SUN Microsystems
Title: "UltraSparc"