A High-Performance Microarchitecture with Hardware-Programmable Functional Units
Rahul Razdan,Michael D. Smith
smith@das.harvard.edu
Abstract
This paper explores a novel way to incorporate hardware-programmable resources
into a processor microarchitecture to improve the performance of
general-purpose applications. Through a coupling of compile-time analysis
routines and hardware synthesis tools, we automatically configure a given set
of the hardware-programmable functional units (PFUs) and thus augment the base
instruction set architecture so that it better meets the instruction set needs
of each applications. We refer to this new class of general-purpose computers
as PRogrammable Instruction Set Computers (PRISC). Although similar in
concept, the PRISC approach differs from dynamically programmable microcode
because in PRISC we define entirely-new primitive datapath operations. In this
paper, we concentrate on the microarchitectural design of the simplest form of
PRISC - a RISC microprocessor with a single PFU that only evaluates
combinational functions. We briefly discuss the operating system and the
programming language compilation techniques that are needed to successfully
build PRISC and, we present performance results form a proof-of-concept study.
With the inclusion of a single 32-bit-wide PFU whose hardware cost is less than
that of a 1 kilobyte SRAM, our study shows a 22% improvement in processor
performance on the SPECint92 benchmarks.
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