Minimizing Branch Misprediction Penalties for Superpipelined Processors
Ching-Long Su, Alvin M. Despain
csu@usc.edu
Abstract
Branch misprediction penalties depend on branch misprediction
rates and branch penalties. Dynamic branch schemes take
advantage of hardware to record and predict branch behavior
at run-time for reducing branch misprediction rates. Static
branch schemes take advantage of scheduling safe instructions
into branch delay slots at compile-time for reducing branch
penalties. This paper evaluates and compares the performance
of various state-of-the-art static and dynamic branch schemes
for super-pipelined processors.
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