High performance architectures have always had to deal with the performance-limiting impact of branch operations. Microprocessor designs are going to have to deal with this problem as well, as they move towards deeper pipelines and support for multiple instruction issue. Branch prediction schemes are often used to alleviate the negative impact of branch operations by allowing the speculative execution of instructions after an unresolved branch. Another technique is to eliminate branch instructions altogether. Predication can remove forward branch instructions by translating the instructions following the branch into predicate form.
This paper analyzes a variety of existing predication models for eliminating
branch operations, and the effect that this elimination has on
the branch prediction schemes in existing processors, including single issue
arc
hitectures
with simple prediction mechanisms, to the newer multi-issue designs with
corresp
ondingly
more sophisticated branch predictors.
The effect on branch prediction accuracy, branch penalty and basic block
size is studied.
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