List of Refereed Publications

• H. Lee, G. Tyson and M. Farrens, "Improving Bandwidth Utilization using Eager Writeback", Journal of Instruction Level Parallelism, vol. 4 (to appear) (January 2002)
• M. Oskin, F. Chong, and M. Farrens, "Using Statistical and Symbolic Simulation for Microprocessor Evaluation", Journal of Instruction Level Parallelism, vol. 3 (to appear) (September 2001)
• H. Lee, G. Tyson and M. Farrens, "Eager Writeback - a Technique for Improving Bandwidth Utilization", Proceedings of the 33rd Annual International Symposium on Microarchitecture, Monterey, CA (December 10-13, 2000), pp. 11-21
• K. Rich and M. Farrens, The Decoupled-Style Prefetch Architecture", Proceedings of the 6th International Euro-Par Conference, Munich, Germany (August 28-September 1, 2000), pp. 989-993.
• K. Rich and M. Farrens, "Code Partitioning in Decoupled Compilers", Proceedings of the 6th International Euro-Par Conference, Munich, Germany (August 28-September 1, 2000), pp. 1008-1017.
• M. Oskin, F. Chong and M. Farrens, "HLS:  Combining Statistical and Symbolic Simulation to Guide Microprocessor Designs", Proceedings of the 27th Annual International Symposium on Computer Architecture, Vancouver, BC (June 12-14, 2000), pp. 71-82.
• P. Sallee, M. Haungs and M. Farrens, "Branch Transistion Rate:  A New Metric for Improved Branch Classification Analysis", Proceedings of the 6th International IEEE Symposium on High Performance Computer Architecture , Toulouse, France (January 10-12, 2000), pp. 241-250.
• M. Oskin, J. Hensley, D. Keen, F. Chong, M. Farrens and A. Chopra, "Exploiting ILP in Page-based Intelligent Memory", Proceedings of the 32nd Annual International Symposium on Microarchitecture, Haifa, Israel (November 16-18, 1999), pp. 208-218.
• J. Rivers, E. Tam, G. Tyson, E. Davidson and M. Farrens, "Utilizing Reuse Information in Data  Cache Management", Proceedings of the 12th ACM International Conference on Supercomputing", Melbourne, Australia (July 13-17, 1998), pp. 449-456.
• G. Tyson, M. Farrens, J. Matthews and A. Pleszkun, "Managing Data Caches using Selective Cache Line Replacement", International Journal of Parallel Processing, vol. 25, no. 3 (June 1997), pp. 213-242.
  
• G. Tyson and M. Farrens, "Evaluating the Effects of Predicated Execution on Branch Prediction" , International Journal of Parallel Processing, vol. 23, no. 1 (1996)
• G. Tyson, M. Farrens, J. Matthews, and A. Pleszkun, "A Modified Approach to Data Cache Management" , Proceedings of the 28th Annual International Symposium on Microarchitecture Ann Arbor, MI (Nov 29-Dec 1, 1995).
• M. Farrens, G. Tyson, and A. Pleszkun, "A Study of Single-Chip Processor/Cache Organizations for Large Numbers of Transistors" , Proceedings of the 21st Annual International Symposium on Computer Architecture, Chicago, IL (April 18-21, 1994).
• G. Tyson, M. Farrens, "Code Scheduling for Multiple Instruction Stream Architectures" , International Journal of Parallel Processing, vol. 22, no. 3 (1994)
• M. Farrens, P. Nico and P. Ng, "A Comparison of Superscalar and Decoupled Access/Execute Architectures" , Proceedings of the 26th Annual International Symposium on Microarchitecture, Austin, Texas (December 1-3, 1993)
• G. Tyson and M. Farrens, "Techniques for Extracting Instruction Level Parallelism on MIMD Architectures" , Proceedings of the 26th Annual International Symposium on Microarchitecture, Austin, Texas (December 1-3, 1993)
• G. Tyson, M. Farrens and A. Pleszkun, "MISC: A Multiple Instruction Stream Computer" , Proceedings of the 25th Annual International Symposium on Microarchitecture, Portland, Oregon (December 1-4, 1992)
• A. Park, M. Farrens and G. Tyson, "Modifying VM Hardware to Reduce Address Pin Requirements" , Proceedings of the 25th Annual International Symposium on Microarchitecture, Portland, Oregon (December 1-4, 1992)
• M. Farrens, A. Park, R. Fanfelle, P. Ng and G. Tyson, "A Partitioned Translation Lookaside Buffer Appraoch to Reducing Address Bandwidth" , Proceedings of the 19th Annual International Symposium on Computer Architecture, Queensland, Australia (May 19-21, 1992)
• M. Farrens, A. Park and A. Woodruff, "CCHIME: A Cache Coherent Hybrid Interconnected Memory Extension" , Proceedings of the 6th International Parallel Processing Symposium, Hollywood, California (March, 1992)
• M. Farrens, B. Wetmore and A. Woodruff, "Alleviation of Tree Saturation in Multistage Interconnection Networks" , Proceedings of Supercomputing '91, Albuquerque, New Mexico (November, 1991)
• J. Becker, A. Park and M. Farrens, "An Analysis of the Information Content of Address Reference Streams" , Proceedings of the 24th Annual International Symposium on Microarchitecture, Albuquerque, New Mexico (November, 1991)
• M. Farrens and A. Park, "Workload and Implementation Considerations for Dynamic Base Register Caching" , Proceedings of the 24th Annual International Symposium on Microarchitecture, Albuquerque, New Mexico (November, 1991)
• M. Farrens and A. Pleszkun, "Strategies for Achieving Improved Processor Throughput" , Proceedings of the 18th Annual International Symposium on Computer Architecture, Toronto, Canada (May 27-30, 1991).
• M. Farrens and A. Park, "Dynamic Base Register Caching: A Technique for Reducing Address Bus Width" , Proceedings of the 18th Annual International Symposium on Computer Architecture, Toronto, Canada (May 27-30, 1991).
• M. Farrens and A. Pleszkun, "Overview of the PIPE Processor Implementation" , Proceedings of the 24th Annual Hawaii International Conference on System Sciences, Kapaa, Kauai (January 9-11, 1991).
• A. Park and M. Farrens, "Address Compression Through Base Register Caching" , Proceedings of the 23th Annual Symposium and Workshop on Microprogramming and Microarchitectures, Orlando, Florida (November 1990)
• M. Farrens and A. Pleszkun, "An Evaluation of Functional Unit Lengths for Single Chip Processors" , Proceedings of the 23th Annual Symposium and Workshop on Microprogramming and Microarchitectures, Orlando, Florida (November 1990)
• M. Farrens and A. Pleszkun, "Improving the Performance of Small On-Chip Instruction Caches" , Proceedings of the 16th Annual International Symposium on Computer Architecture, Jerusalem, Israel (June 1989).
• M. Farrens and A. Pleszkun, "Implementation of the PIPE Processor" , Computer, January 1991
• A. Pleszkun and M. Farrens, "An Instruction Cache Design for Use with a Delayed Branch" Advanced Research in VLSI: Proceedings of the Fourth MIT Conference , April 1986

 

List of Unrefereed Publications (Tech Reports)

• Matthew Farrens,  "The Architecture Curriculum at UC-Davis" , IEEE Technical Committee on Computer Architecture, February 1999, pp. 28-30.
• Matthew Farrens,  "The Architecture Curriculum at UC-Davis" ,  presented at the Workshop on Computer Architecture Education, held in conjunction with the 25th Annual International Symposium on Computer Architecture, Barcelona, Spain, June 1998.
• Matthew Farrens, Timothy Heil, James E. Smith and Gary Tyson, "Restricted Dual Path Execution" , Computer Science Department Technical Report CSE-97-18, University of California at Davis, Davis, California (November 1997).
• Gary Tyson, Matthew Farrens, Kevin Rich, and Andrew Pleszkun, "Reducing the Branch Penalty of Mispredicted Short Forward Branches" , Computer Science Department Technical Report CSE-95-7, University of California at Davis, Davis, California (August 1995).
• Gary Tyson, Matthew Farrens, John Matthews, and Andrew Pleszkun, "A New Approach to Cache Management" , Computer Science Department Technical Report CSE-95-6, University of California at Davis, Davis, California (August 1995).
• M. Farrens, G. Tyson and A. Pleszkun, "A Study of Single-Chip Processor/Cache Organizations for Large Numbers of Transistors" , Computer Science Department Technical Report CSE-92-24, University of California at Davis, Davis, California (December 1992).
• G. Tyson, M. Farrens and A. Pleszkun, "MISC: A Multiple Instruction Stream Computer" , Computer Science Department Technical Report CSE-92-23, University of California at Davis, Davis, California (December 1992).
• M. Farrens, A. Park, R. Fanfelle, P. Ng and G. Tyson, "A Partitioned Translation Lookaside Buffer Approach to Reducing Address Bandwidth" , Computer Science Department Technical Report CSE-91-37, University of California at Davis, Davis, California (November 1991).