Micro-28 Advance Program

For the past 27 years, the annual MICRO conference has provided a key venue for the dissemination of ideas and advances in the field of computer microarchitecture research. MICRO has recently become the premier forum for discussing and debating issues relating to instruction-level parallelism; and I am pleased to report that this trend has continued this year. We received an unprecedented number of outstanding submissions, each of which was rigorously reviewed by an average of 5.6 qualified individuals (both program committee members and outside reviewers). Based on these reviews, the program committee has put together a strong program of 22 long and 15 short papers, covering all facets of high-performance CPU design and compilation.

In addition to the paper presentations, Micro'28 will feature three invited lectures. These presentations will cover micro-architecture topics ranging from commercial state of the art microprocessors to alternative ways of looking at high-performance CPUs. In particular, I would like to thank Richard Baum for agreeing to give the keynote speech. His visions will be of great interest in their own right.

For the first time the Micro conference has come to the upper midwest and to lovely Ann Arbor, Michigan. Ann Arbor has been selected as the host city because of its central location and proximity to the many outstanding universities in the region (starting with the University of Michigan). [EDITOR'S NOTE - Trev, can I say something here about how mild the weather will be in late November, or is it actually pretty beastly at times?]

In addition to the excellent slate of presentations, MICRO is famous for it's opportunities for personal interaction with leading researchers in the area. I invite you to join us in Ann Arbor, and I look forward to personally greeting each and every one of you!

Trevor Mudge
General Chair, Micro 28
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Tuesday, November 28

6:30- 8:00 Welcoming Reception

Wednesday, November 29

8:00- 8:15 Welcoming Remarks: Trevor Mudge, General Chair

8:15- 9:15 Kenote Address: Richard Baum, IBM

Title:""

9:30-10:45 Session 1: Branch Prediction I

"Performance Issues in Correlated Branch Prediction Schemes" , Nicolas Gloy, Michael D. Smith, Cliff Young - Harvard (USA)

"Dynamic Path-Based Branch Correlation" , Ravi Nair, IBM T.J. Watson Research Center (USA)

"The Predictability of Libraries" , Brad Calder, Dirk Grunwald - University of Colorado, Boulder, Amitabh Srivastava, DEC Western Research Lab (USA)

11:00-12:15 Session 2: ILP Compilation I

"The Performance Impact of Incomplete Bypassing in Processor Pipelines ", Pritpal S. Ahuja, Douglas W. Clark, Anne Rogers - Princeton University (USA)

"Efficient Instruction Scheduling Using Finite State Automata" , Vasanth Bala - HP Labs, Norman Rubin, DEC (USA)

"Critical Path Reduction for Scalar Programs" , Michael Schlansker, Vinod Kathail - HP Labs (USA)

1:45-3:00 Session 3: Memory System Issues

"A Limit Study of Local Memory Requirements Using Value Reuse Profiles", Andrew S. Huang, John P. Shen - Carnegie Mellon University (USA)

"Zero-Cycle Loads: Microarchitecture Support for Reducing Load Latency", Todd M. Austin, Gurindar S. Sohi - University of Wisconsin, Madison (USA)

"A Modified Approach to Data Cache Management", Gary Tyson - UC Riverside, Matthew Farrens, John Matthews - UC Davis, Andrew Pleszkun - University of Colorado, Boulder (USA)

3:15-4:15 Session 4: Topics in Software Pipelining and ILP Compilation

"Petri Net versus Modulo Scheduling for Software Pipelining", V.H. Allan, U.R. Shah, K.M. Reddy - Utah State University (USA)

"Modulo Scheduling with Multiple Initiation Intervals", Nancy J. Warter-Perez, Noubar Partamian - California State University, Los Angeles (USA)

"Effective Scheduling of Directed Acyclic Graphs under Register Constraints ", Balas Natarajan, Michael Schlansker - HP Labs (USA)

"Improving Instruction-Level Parallelism by Loop Unrolling and Dynamic Memory Disambiguation", Jack W. Davidson, Sanjay Jinturkar - University of Virginia (USA)

8:00-10:00 Business Meeting

Thursday, December 1

8:00- 9:00 Invited Speaker: Tom Jermoluk, Silicon Graphics

Title:""

9:15-10:05 Session 5: Data flow and Multithreading Architectures

"Self-Regulation of Workload in the Manchester Data-Flow Computer", John R. Gurd, David F. Snelling - University of Manchester (UK)

"The M-Machine Multicomputer", Marco Fillo, Stephen W. Keckler, William J. Dally, Nicholas P. Carter, Andrew Chang, Yevgeny Gurevich, Whay S. Lee - MIT AI Laboratory and Laboratory for Computer Science (USA)

10:20-11:35 Session 6: ILP Compilation II

"Region-Based Compilation: An Introduction and Motivation", Richard E. Hank, Wen-mei W. Hwu - University of Illinois, B. Ramakrishna Rau - HP Labs (USA)

"An Experimental Study of Several Cooperative Register Allocation and Instruction Scheduling Strategies", Cindy Norris, Lori L. Pollock - University of Delaware (USA)

"Predicated Register Allocation", Alexandre E. Eichenberger, Edward S. Davidson - University of Michigan (USA)

11:50-12:20 Session 7: Analysis of Branching Architecture

"Branch Aliasing in Branch Target Buffers", Barry Fagin - U.S. Air Force Academy, Kathryn Russell - Lockheed Sanders, Inc. (USA)

"A System Level Perspective on Branch Architecture Performance", Brad Calder, Dirk Grunwald - University of Colorado, Boulder, Joel Emer - DEC (USA)

1:45-2:35 Session 8: Software and Hardware Object Code Translation

"Dynamic Rescheduling: A Technique for Object Code Compatibility in VLIW Architectures", Thomas M. Conte, Sumedh W. Sathaye - North Carolina State University (USA)

"Improving CISC Instruction Decoding Performance Using a Fill Unit", Mark Smotherman, Manoj Franklin - Clemson University (USA)

3:00-3:45 Session 9: Data Prefetching

"SPAID: Software Prefetching In Pointer and Call-Intensive Environments", Mikko H. Lipasti, William J. Schmidt, Steven R. Kunkel, Robert R. Roediger - IBM (USA)

"An Effective Programmable Prefetch Engine for On-Chip Caches", Tien-Fu Chen - National Chung Cheng University (Taiwan)

"Cache Miss Heuristics and Preloading Techniques for General-Purpose Programs", Toshihiro Ozawa - Fujitsu Laboratories Ltd., Shin'ichiro Nishizaki - Fujitsu Social Science Laboratory Ltd., Yasunori Kimura - Fujitsu Laboratories Ltd. (Japan)

4:00-5:00 Panel

Organizer: Jim Bondi - Texas Instruments

Title: "Design Directions for Future Processors"

6:30-9:00 Conference Dinner

Friday, December 1nd

8:00-9:00 Invited Speaker: Fred Pollack, Intel

Title:""

9:15-10:00 Session 10: Branch Prediction II

"Alternative Implementations for Hybrid Branch Predictors", Po-Yung Chang, Eric Hao, Yale N. Patt - University of Michigan (USA)

"Control Flow Prediction with Tree-Like Subgraphs for Superscalar Processors", Simonjit Dutta, Manoj Franklin - Clemson University (USA)

"The Role of Adaptivity in Two-level Adaptive Branch Prediction", Stuart Sechrest, Chih-Chieh Lee, Trevor N. Mudge - University of Michigan (USA)

10:15-11:00 Session 11: Multithreading and Superscalar Design studies

"Design of Storage Hierarchy in Multithreaded Architectures", Lucas Roh - Argonne National Laboratory, Walid A. Najjar - Colorado State University (USA)

"An Investigation of the Performance of Various Instruction-Issue Buffer Topologies", Stephan Jourdan, Pascal Sainrat, Daniel Litaize - Institut de Recherche en Informatique de Toulouse, Universite Paul Sabatier (France)

"Decoupling Integer Computation in Superscalar Processors", Subbarao Palacharla, J.E. Smith - University of Wisconsin, Madison (USA)

11:15-12:30 Session 12: Architectural Features for ILP

"Exploiting Short-Lived Variables in Superscalar Processors", Luis A. Lozano C., Guang R. Gao - McGill University (Canada)

"Partitioned Register File for TTAs", Johan Janssen, Henk Corporaal - Delft University of Technology (Netherlands)

"Disjoint Eager Execution: An Optimal Form of Speculative Execution", Augustus K. Uht, Vijay Sindagi - University of Rhode Island (USA)

1:45-3:00 Session 13: Software Pipelining II

"Unrolling-Based Optimizations for Software Pipelining", Daniel M. Lavery, Wen-mei W. Hwu - University of Illinois (USA)

"Stage Scheduling: A Technique to Reduce the Register Requirements of a Modulo Schedule", Alexandre E. Eichenberger, Edward S. Davidson - University of Michigan (USA)

"Hypernode Reduction Modulo Scheduling", Josep Llosa, Mateo Valero, Eduard Ayguade, Antonio Gonzalez - Universitat Politecnica de Catalunya. Barcelona (Spain)

3:00-3:15 Closing Remarks

Saturday, December 2

Tutorials: