The M-Machine Multicomputer
Marco Fillo, Stephen W. Keckler, William J. Dally, Nicholas P. Carter,
Andrew Chang, Yevgeny Gurevich, Whay S. Lee
Abstract
The M-Machine is an experimental multicomputer being developed to test
architectural concepts motivated by the constraints of modern
semiconductor technology and the demands of programming systems. The
M-Machine computing nodes are connected with a 3-D mesh network; each
node is a multithreaded processor incorporating 12 function units,
on-chip cache, and local memory. The multiple function units are used
to exploit both instruction-level and thread-level parallelism. A user
accessible message passing system yields fast communication and
synchronization between nodes. Rapid access to remote memory is
provided transparently to the user with a combination of hardware and
software mechanisms. This paper presents the architecture of the
M-Machine and describes how its mechanisms maximize both single thread
performance and overall system throughput.
Keywords
parallel computer architecture, instruction level,
parallelism, multithreading, message passing, memory coherency
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