An Investigation of the Performance of Various Instruction-Issue
Stephan Jourdan, Pascal Sainrat, Daniel Litaize
In out-of-order issue superscalar microprocessors, instructions must be
buffered before their issuing. This buffer can be either unified (one
buffer linked to all units), distributed among the units as in the
PowerPC620, or semi-unified (a few buffers each shared by several
units) as in the MIPS R10000. Of course, the size of this buffer also
plays a leading role in the performance of the processor. Intensive
trac-driven simulations on the SPEC92 suite have been made in order to
determine the best designs and cost-effective choices are pointed out
according to the degree of the processor.
Instruction-Level Parallelism, Superscalar Architecture,
Out-of-Order and Speculative Execution, and Instruction-Issue Buffer.
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