ECS154A Homework #2

Assignment (Written):

  1. The following 12 bit patterns are received from memory.

    1. 0 0 0 0 1 1 0 1 0 1 1 1
    2. 0 1 1 1 1 0 0 0 1 0 0 0

    Assuming the same single error correcting code we used in class, give the correct 8-bit data value for each pattern. Show Your Work.

  2. Consider the timing diagram in Figure P7.1. Assuming that the D and Clock inputs shown are applied to the circuit in figure 7.12, draw waveforms for the Qa, Qb, and Qc signals.
  3. Given an 80MHZ clock signal, derive a circuit using only DFF's that will generate a 40MHZ and a 20MHZ signal. Draw timing diagrams for all 3 clock signals, assuming reasonable delays.
  4. Show how an RSFF can be built using only a DFF and some other logic.
  5. Show how a JKFF can be built using only a TFF and some other logic.
  6. For the flip-flops in the counter in figure 7.25, assume that the setup time is 6ns, the hold time is 2ns, and the propagation delay through a flip-flop is 2ns. Assume that each AND, XOR and 2-1 Mux has a propagation delay of 1ns. What is the maximum clock frequency that can be used that will ensure correct operation of the circuit?
  7. A circuit for a gated D latch is shown in figure p7.7. Assume the NAND has a propagation delay of 3ns and the inverter propagation delay is 1ns. Complete the timing diagram given in the figure, which shows the signal values with a 1ns resolution.
  8. Given the following information:

    9. The propagation delay through a DFF is 8ns
    The setup time for a DFF is 3ns
    The hold time for a DFF is 2ns
    The delay through an AND gate is 4ns
    The delay through a MUX is 5ns
    X, Y and SEL are fixed and do not change

    Find the worst case path through the following circuit.


Assignment (Logisim):

  1. Implement in Logisim the circuit to calculate the check bits and correct incoming errors using the format we used in class. You can check your work by making sure the bit patterns of problem 3 come out correctly. Use the following naming convention: 
    (Left to right, most significant to least significant bit)
		msb                        lsb  
Input Pins:  	D7  D6  D5  D4  D3  D2  D1  D0	-- Data Bits
		C3  C2  C1  C0			-- Check Bits
Output Pins: 	Z7  Z6  Z5  Z4  Z3  Z2  Z1  Z0	-- Output Data Bits
Filename: sec
  2. Design a four-bit synchronous counter with parallel load. Use T flip-flops, instead of the D flip-flops used in section 7.9.3.
  3. Design a 3-bit up/down counter using D flip-flops. It should include a control input called !UP/Down. If !UP/Down=0, then the circuit should behave as an up-counter. If !UP/Down=1, then the circuit should behave as a down-counter.