Checking and Compiling Your Design

  Once you have completed entering your design and have set the name of the project, you may check your design for errors using the command:

File -> Project -> Save & Check

If your design has an error, highlight the error message using the left mouse button and press the Locate button to view the location of the error in your design file.

If your design has no errors or warnings, you may then proceed to compile your design. There are two different types of simulation that can be performed on the design: functional and timing. Each type of simulation requires a separate compilation. Functional simulation allows you to check for logical errors in your circuit. Timing analysis is used to determine the path delays in your circuit and helps to determine the maximum clock frequency at which sequential circuits can operate.

For a functional simulation, select the option:

Processing -> Functional SNF Extractor

If you want the nodes in your simulation to maintain the same names as the labels you used for the wires, you should also select the option:

Processing -> Preserve All Node Name Synonyms

To compile your design for the functional simulation, use the command:

File -> Project -> Save & Compile

You may also compile your design by pressing the Start button in the Compiler window. If your design compiles correctly, a Simulator Netlist File (.snf) containing all of the nodes in your circuit will be created.

To compile your design for a timing analysis, select the option:

Processing -> Timing SNF Extractor

And compile by pressing the Start button in the Compiler window or by using the command:

File -> Project -> Save & Compile