Efficient Instruction Scheduling Using Finite State Automata

Vasanth Bala, Norman Rubin


In this paper we present a method based on finite state automata, to conveniently model the state of the processor's pipeline resources during instruction scheduling, as well as techniques for simplifying certain complicated code motions that are essential for efficient instruction scheduling across basic blocks. We also discuss the implementation of our technique in a production compiler, and give results on automata we have developed for various processors.


structural hazard, global instruction scheduling, finite state automaton, pipelined processor, compiler optimization

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