Facilitating Superscalar Processing via a Combined Static/Dynamic Register
Renaming Scheme
Eric Sprangle, Yale Patt
patt@eecs.umich.edu
Abstract
A superscalar implementation of a conventional instruction
set architecture (ISA) requires N(N-1) comparators to
determine dependencies between the N instructions issuing
concurrently (2) and 2N register file read ports to handle
the 2 operands that each instruction can potentially source.
On the other hand, if the compiler is allowed to specify
part of the renaming tag, we show that we can eliminate
the comprators needed to detect data dependencies between
instructions issuing concurrently, and we can reduce the
number of read ports from 16 to 7 without losing performance.
Finally, we show that this approach more efficiently
implements predicated execution than can be done with a
conventional ISA on a machine that renames registers.
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