[FaTP94]
        M. Farrens,  G.  Tyson  and  A.  Pleszkun,  "A  Study  of  Single-Chip
        Processor/Cache  Organizations  for  Large  Numbers  of  Transistors",
        Proceedings of the 21st Annual  International  Symposium  on  Computer
        Architecture, Chicago, IL (April 18-21, 1994).

[TyFa93]
        G. Tyson and M. Farrens, "Techniques for Extracting Instruction  Level
        Parallelism  on  MIMD  Architectures",  Proceedings of the 26th Annual
        International Symposium on Microarchitecture, Austin, Texas  (December
        1-3, 1993), pp. 128-137.

[FaNN93]
        M. Farrens, P. Nico and  P.  Ng,  "A  Comparison  of  Superscalar  and
        Decoupled  Access/Execute  Architectures",  Proceedings  of  the  26th
        Annual International Symposium  on  Microarchitecture,  Austin,  Texas
        (December 1-3, 1993), pp. 100-103.

[FaTP92]
        M. Farrens, G. Tyson and A. Pleszkun, "MISC:  A  Multiple  Instruction
        Stream  Computer",  Computer  Science Department Technical Report CSE-
        92-23, University of California at Davis, Davis,  California (December
        1992).

[PaFT92]
        A. Park, M. Farrens and G. Tyson, "Modifying  VM  Hardware  to  Reduce
        Address   Pin   Requirements",   Proceedings   of   the   25th  Annual
        International  Symposium  on   Microarchitecture,   Portland,   Oregon
        (December 1-4, 1992), pp. 210-213.

[FPFN92]
        M. K.  Farrens,  A.  Park,  R.  Fanfelle,  P.  Ng  and  G.  Tyson,  "A
        Partitioned  Translation Lookaside Buffer Appraoch to Reducing Address
        Bandwidth",  Proceedings  of  the  Nineteenth   Annual   International
        Symposium  on Computer Architecture, Queensland, Australia (May 19-21,
        1992), pp. 435.

[FaPa92]
        M.  Farrens  and  A.  Park,   "CCHIME:   A   Cache   Coherent   Hybrid
        Interconnected   Memory   Extension",   Sixth  International  Parallel
        Processing Symposium, Hollywood, CA (March 1992), pp. 573-577.

[FaWW91]
        M. K. Farrens, B. R. Wetmore and A. G. Woodruff, "Alleviation of  Tree
        Saturation  in  Multistage  Interconnection  Networks", Proceedings of
        Supercomputing '91, Albuquerque, New Mexico  (November  18-20,  1991),
        pp. 400-409.

[FaPa91]
        M. Farrens and A. Park, "Workload  and  Implementation  Considerations
        for  Dynamic  Base  Register  Caching", Proceedings of the 24th Annual
        International Symposium on Microarchitecture, Albuquerque, New  Mexico
        (November 18-20, 1991), pp. 62-68.

[BePF91]
        J. Becker, A. Park and M. Farrens, "An  Analysis  of  the  Information
        Content  of Address Reference Streams", Proceedings of the 24th Annual
        International Symposium on Microarchitecture, Albuquerque, New  Mexico
        (November 18-20, 1991), pp. 19-24.

[FaPl91a]
        M.  Farrens  and  A.  Pleszkun,  "Strategies  for  Achieving  Improved
        Processor   Throughput",   Proceedings   of   the   Eighteenth  Annual
        International Symposium on Computer Architecture, Toronto, Canada (May
        27-30, 1991), pp. 362-369.

[FaPa91]
        M. Farrens and A. Park, "Dynamic Base Register Caching:   A  Technique
        for  Reducing Address Bus Width", Proceedings of the Eighteenth Annual
        International Symposium on Computer Architecture, Toronto, Canada (May
        27-30, 1991), pp. 198-207.

[FaPl91]
        M. Farrens and A. Pleszkun, "Implementation of  the  PIPE  Processor",
        Computer(January 1991), pp. 65-70.

[FaPl91b]
        M.  Farrens  and  A.  Pleszkun,  "Overview  of  the   PIPE   Processor
        Implementation",  Proceedings  of the 24th Annual Hawaii International
        Conference on System Sciences, Kapaa, Kauai (January 9-11, 1991),  pp.
        433-443.

[PaFa90]
        A. Park and M. Farrens, "Address  Compression  Through  Base  Register
        Caching",  Proceedings  of  the  23rd Annual Symposium and Workshop on
        Microprogramming and Microarchitectures,  Orlando,  Florida  (November
        27-29, 1990), pp. 193-199.

[FaPl90]
        M. Farrens and A. Pleszkun, "An Evaluation of Functional Unit  Lengths
        for  Single Chip Processors", Proceedings of the 23rd Annual Symposium
        and Workshop  on  Microprogramming  and  Microarchitectures,  Orlando,
        Florida (November 27-29, 1990), pp. 209-215.

[FaPl89]
        M. K. Farrens and A. R. Pleszkun, "Improving the Performance of  Small
        On-Chip  Instruction  Caches",  Proceedings  of  the  Sixteenth Annual
        International Symposium on Computer Architecture,   vol.  17,  no.  3
        (June 1989), pp. 234-241.

[PlFa86]
        A. R. Pleszkun and M. K. Farrens, "An Instruction Cache Design for Use
        with a Delayed Branch", Advanced Research in VLSI:  Proceedings of the
        Fourth MIT Conference(April 1986).