MAX+PLUS II Tips

Primitives

and2, or2, nand2, nor2, xor, not: Standard gates. In general, an n input component is specified by placing n after the name of the component, e.g. a four-input and gate is specified as and4.

tri: Tri-state buffer. When the enable input is set to 0, the device is in a high-impedence state (output is disconnected). When the enable input is set to 1, the input of the device passes to the output. Normally, a number of tri-state buffers will have their outputs connected to a single wire or bus. It is important to make sure that exactly one of these tri-state buffers is enabled at any time. If more than one is enabled, then a conflict will occur on the wire. If none of the tri-state buffers are enabled, then the output will be an unspecified value (neither 0 nor 1), which is an undesirable condition, and errors may propagate through the circuit.

gnd: Ground component. This component can be used to set the value of a wire or a bus to 0.

vcc: Vcc component. This component can be used to set the value of a wire or a bus to 1.

input: An input pin.

output: An output pin.

Flip-flops

dff: D flip-flop. The ">" input is the clock input. The flip-flop triggers on the rising clock edge. The PRN input is used to "preset" the flip-flop. If PRN = 0, the output Q is set to 1 on the following rising clock edge. The CLRN is used to "clear" the flip-flop. If CLRN = 0, the output Q is set to 0 on the following rising clock edge.

   Inputs     Next State
  PRN CLRN D     Q+
---------------------
   0   1   X     1     
   1   0   X     0     

   1   1   0     0
   1   1   1     1

dffe: D flip-flop with write enable. This flip-flop is similar to the dff component with the exception of an ENA input. The ENA input enables the flip-flop. When ENA = 1, the value at input D will be loaded to the flip-flop and sent to the output on the following rising clock edge.

74377b: Octal D flip-flop with write enable. This component consists of eight dffe components with an inverted EN input. If EN = 1, the flip-flops are disabled, and if EN = 0, the flip-flops are enabled (they will load the input values on the next clock cycle).

74374b: Octal D flip-flop with output enable. This component consists of eight D flip-flops with tri-state outputs. If OEN = 0, the output Q will reflect the values stored in the flip-flops. If OEN = 1, the outputs will be in a high-impedence state (outputs are disconnected). This component does not have a write enable input. Therefore, the value of the inputs will always be loaded into the flip-flop on the rising edge of the clock.

Comparatos

7485: This is a 4-bit comparator. Given two 4-bit binary numbers A[3..0] and B[3..0], the output ALBO is set to 1 iff A is less than B, the output AEBO is set to 1 iff A is equal to B, and the output AGBO is set to 1 iff A is greater than B. The ALBI, AEBI, and AGBI inputs are used to cascade multiple comparators to create larger (e.g. 8-bit) comparators. If you are only comparing 4-bit numbers, then ALBI and AGBI should be set to 0, and AEBI should be set to 1.

Decoders

dec38: This is a 3-to-8 decoder. The SENSE input determines whether the output is active high or active low. If SENSE = 0, the output is active low (exactly one output will be 0, and the other outputs will be 1). If SENSE = 1, the output is active high (exactly one output will be 1, and the other outputs will be 0). The INHB input disables the decoder. If INHB = 1 and SENSE = 0, all of the outputs will be 1, and if INHB = 1 and SENSE = 1, all of the outputs will be 0. The truth table is as follows:

       Inputs                        Outputs
SENSE  INHB  S2 S1 S0     Y0  Y1  Y2  Y3  Y4  Y5  Y6  Y7 
---------------------     ------------------------------- 
  0      1    X  X  X      1   1   1   1   1   1   1   1
  1      1    X  X  X      0   0   0   0   0   0   0   0

  0      0    0  0  0      0   1   1   1   1   1   1   1
  0      0    0  0  1      1   0   1   1   1   1   1   1
  0      0    0  1  0      1   1   0   1   1   1   1   1
  0      0    0  1  1      1   1   1   0   1   1   1   1
  0      0    1  0  0      1   1   1   1   0   1   1   1
  0      0    1  0  1      1   1   1   1   1   0   1   1
  0      0    1  1  0      1   1   1   1   1   1   0   1
  0      0    1  1  1      1   1   1   1   1   1   1   0

  1      0    0  0  0      1   0   0   0   0   0   0   0
  1      0    0  0  1      0   1   0   0   0   0   0   0
  1      0    0  1  0      0   0   1   0   0   0   0   0
  1      0    0  1  1      0   0   0   1   0   0   0   0
  1      0    1  0  0      0   0   0   0   1   0   0   0
  1      0    1  0  1      0   0   0   0   0   1   0   0
  1      0    1  1  0      0   0   0   0   0   0   1   0
  1      0    1  1  1      0   0   0   0   0   0   0   1

74138: This is a 3-to-8 decoder with active low outputs. The G1, G2AN, and G2BN are enable inputs. G1 should be set to 1 using the vcc component, and G2AN and G2BN should be set to 0 using the gnd component. The truth table for the device is shown below.

   Inputs                Outputs
   C B A     Y0N Y1N Y2N Y3N Y4N Y5N Y6N Y7N
   -----     ------------------------------- 
   0 0 0      0   1   1   1   1   1   1   1
   0 0 1      1   0   1   1   1   1   1   1
   0 1 0      1   1   0   1   1   1   1   1
   0 1 1      1   1   1   0   1   1   1   1
   1 0 0      1   1   1   1   0   1   1   1
   1 0 1      1   1   1   1   1   0   1   1
   1 1 0      1   1   1   1   1   1   0   1
   1 1 1      1   1   1   1   1   1   1   0

Multiplexers

21mux: Standard 2-to-1 multiplexer. If select input S = 0, then data input B is selected. If select input S = 1, then data input A is selected.

81mux: An 8-to-1 multiplexer with tri-state outputs. The GN input should be set to 0 using the gnd component to enable the outputs.

   Inputs    Outputs
   C B A     Y   WN
   -----     ------- 
   0 0 0     D0  D0'
   0 0 1     D1  D1' 
   0 1 0     D2  D2' 
   0 1 1     D3  D3'
   1 0 0     D4  D4'
   1 0 1     D5  D5'
   1 1 0     D6  D6'
   1 1 1     D7  D7'

Bus multiplexers

2x8mux: This is an 8-bit, 2-to-1 multiplexer. When the SEL input is set to 0, the B[7..0] input is sent to the Y[7..0] output. When the SEL input is set to 1, the A[7..0] input is sent to the Y[7..0].

busmux: This is an n-bit, 2-to-1 multiplexer, where n can be set to any value. This componenent can be found in the mega_lpm library.

lpm_mux: This is an n-bit, m-to-1 multiplexer, where n and m can be set to any value. This component can be found in the mega_lpm library, and the procedure for using this component is outlined below.

Creating bus multiplexers using lpm_mux

1.: Select the lpm_mux component from the mega_lpm library. A window will show up, allowing you to edit the parameters of the mux.
2.: Click on LPM_SIZE in the box at the bottom of the window.
3.: In the Parameter box, replace <none> with the desired number of mux inputs (e.g. 4 for a 4-to-1 mux, 8 for an 8-to-1 mux, etc.).
4.: Click the "Change" button.
5.: Click on LPM_WIDTH in the box at the bottom of the window.
6.: In the Parameter box, replace <none> with the desired number of muxs (e.g. if you have buses A[7..0], B[7..0], C[7..0], and D[7..0], the LPM_WIDTH should be set to 8).
7.: Click on the "Change" button.
8.: Click on the "OK" button. The mux componenent will now show up in the graphic editor window.
9.: Connect buses and pins to the component and label them as in the following diagram. The figure is for a 4-to-1 mux. For an 8-to-1 mux, there would be an extra select input and four additional data input buses.
10.: Use the command File -> Create Default Symbol.