Answers

Quiz 1:

1. Embedded, Server, Desktop
2. The density of transisitors increases Quadratically with a linear decrease in feature size.
3. DRAMS drop in cost faster than microprocessors
4. yield problems
5. MIPS are a bad measure of performance
6. Doesn’t track or predict execution time
7. CPU = (instt/program) * (cyclec/instt) * (time/cycle)
8. Embedded processor with worst performance per watt = AMD Elan5C520
9. Standards Performance Evaluation Cooperative

Quiz 2 :

1. register-register, regiser-memory, load-store
2. Optimized programs execute roughly 25% to (90)% fewer instructions
than unoptimized programs. 
3. 4 different types of control flow changes: Conditional Branches, Jumps, Calls, Returns
4. Fixed Point
5. No
6. (25%) percent of data transfers and ALU operations have an immediate
operand? 
7. Variable length
8. No. A small number of instructions tend to be executed frequently.
9. 2 - BCD can only represent 00 through 99.
10. SIMD : Single Instruction, Multiple Data
11. stack machines are Difficult to pipeline
12. The measurements reported in the book are (static, dynamic) measurements 
 
 

Quiz-3:

1. Number of pipeline stages
2. ID, EX, MEM, WB (1/2 point each)
3. ALU, Load/Store, Branch & Jump
4. Structural, Data, Control
5. RAW, WAR, WAW
6. Bypassing/forwarding
7. Interrupts/exceptions

8. Precise Interrupts

Quiz-4:

1.  Spacial locality, Temporal locality
2.  Access and execute
3.  Tolerate
4.  Compulsory, Capacity, Conflict, Coherence
5.  Victim cache is small cache that holds lines that have been evicted
        from the main cache.  It can be thought of as extending the
        associativity of those lines in the main cache that are having
        conflict misses, reducing the performance penalty.
        (The students do not need to have all this, but this is the essence
        of what they should say.)
6.  Prefetching is one technique that can be used to reduce Compulsory misses
7.  Direct-mapped is faster
8.  Fully associative will have higher hit rate

Quiz-5:
1.  DDR = Double Data Rate
2.  To make all processes/users think they have the entire machine to
    themselves (have the entire set of memory addresses available to them).
3.  SISD, SIMD, MISD, MIMD
4.  TLB stands for Translation Lookaside Buffer - it is a "page table cache"
    (A cache of recent mappings from virtual to physical addresses).
5.  SMT = Simultaneous Multi-Threaded
6.  Cache coherence is the need to make sure that the cache in a system
    contains the same values as the memory behind it (or alternatively, that
    each cache has the freshest, most recent copy of a shared value).
7.  PIM = Processor In Memory