ECS154A Homework #2

• Written homework due by 4:30 PM on Wednesday, January 28th
• Programming assignments must be submitted by midnight on Wednesday, January 28th.
  

Assignment (Written):

1. Do Problem 5.12 in the book
2. Do Problem 5.15 in the book
3. The following 12 bit patterns are received from memory.


1. 0 0 0 0 1 1 0 1 0 1 1 1
2. 0 1 1 1 1 0 0 0 1 0 0 0

Assuming the same single error correcting code we used in class, give the correct 8-bit data value for each pattern. Show Your Work.


4. Do Problem 7.1 in the book
5. Given a 60MHZ clock signal, derive a circuit using only DFF's that will generate a 30MHZ and a 15MHZ signal. Draw timing diagrams for all 3 clock signals, assuming reasonable delays.
6. Show how an RSFF can be built using only a DFF and some other logic.
7. Show how a JKFF can be built using only a TFF and some other logic.
8. For the flip-flops in the counter in figure 7.25, assume that the setup time is 4ns, the hold time is 2ns, and the propagation delay through a flip-flop is 2ns. Assume that each AND, XOR and 2-1 Mux has a propagation delay of 1ns. What is the maximum clock frequency that can be used that will ensure correct operation of the circuit?
9. Do Problem 7.35 in the book, only assume that a NAND has a propagation delay of 2ns (the inverter propagation delay is still 1ns).

Assignment (Quartus):

1. Do Problem 5.18 in the book and implement the circuit in Quartus
2. Do Problem 7.15 in the book
3. Implement in Quartus the circuit to calculate the check bits and correct incoming errors using the format we used in class. You can check your work by making sure the bit patterns of problem 3 come out correctly. Use the following naming convention:

    (Left to right, most significant to least significant bit)
               msb                   lsb  
   Input Pins:  D7 D6 D5 D4 D3 D2 D1 D0 -- Data Bits
                            C3 C2 C1 C0 -- Check Bits
   Output Pins: Z7 Z6 Z5 Z4 Z3 Z2 Z1 Z0 -- Output Data Bits
   Filename: sec
   



4. Design a 3-bit ALU using Quartus. Each bit cell should be able to do ADD, SUB, AND, NOT and OR. In addition, the adder should use Carry-Lookahead to improve performance. Your 3-bit ALU should employ group carry lookahead, with group size of 3 and ripple carry between groups. (In other words, correctly generate the carry out of the first group). You are to assume that all arithmetic operations are on 2's compliment numbers. The NOT function should occur on the A inputs.
   The selector/control bits: AND=00, OR=11, NOT=10, ADD/SUB=01 Use the following naming convention:

    (Left to right, most significant to least significant bit)
               msb             lsb 
   Input Pins:  B2 B1 B0  -- B operand
   		A2 A1 A0  -- A operand
                            S1 S0  -- The selector lines (desired operation) 
                              CIN  -- The Carry into the bottom cell
   Output Pins: C2 C1 C0  -- Result
   Filename: alu