ECS154A Homework #2

Assignment (Written):

  1. The following 12 bit patterns are received from memory.

    1. 0 0 0 0 1 1 0 1 0 1 1 1
    2. 0 1 1 1 1 0 0 0 1 0 0 0

    Assuming the same single error correcting code we used in class, give the correct 8-bit data value for each pattern. Show Your Work.
  2. Show how an RSFF can be built using only a DFF and some other logic.
  3. Show how a JKFF can be built using only a TFF and some other logic.
  4. Derive a minimal state table for a single-input and single-output Moore-type FSM that produces an output of 1 if in the input sequence it detects either 110 or 101 patterns. Overlapping sequences should be detected.
  5. Repeat the previous problem for a Mealy-type FSM.
  6. A circuit for a gated D latch is shown in figure p7.7. Assume the NAND has a propagation delay of 3ns and the inverter propagation delay is 1ns. Complete the timing diagram given in the figure, which shows the signal values with a 1ns resolution.
  7. For the flip-flops in the counter in figure 7.25, assume that the setup time is 6ns, the hold time is 2ns, and the propagation delay through a flip-flop is 2ns. Assume that each AND, XOR and 2-1 Mux has a propagation delay of 1ns. What is the maximum clock frequency that can be used that will ensure correct operation of the circuit?
  8. Given the following information:

    9. The propagation delay through a DFF is 8ns
    The setup time for a DFF is 3ns
    The hold time for a DFF is 2ns
    The delay through an AND gate is 4ns
    The delay through a MUX is 5ns
    X, Y and SEL are fixed and do not change

    Find the worst case path through the following circuit.


Assignment (Logisim):

  1. A given FSM has an input, w, and an output, z. During four consecutive clock pulses, a sequence of four values of the w signal is applied. Derive a state table for the FSM that produces z = 1 when it detects that either the sequence w : 0010 or w : 1110 has been applied; otherwise, z = 0. After the fourth clock pulse, the machine has to be again in the reset state, ready for the next sequence. Minimize the number of states needed.

  2. Implement in Logisim the circuit to calculate the check bits and correct incoming errors using the format we used in class. You can check your work by making sure the bit patterns of problem 1 come out correctly. Use the following naming convention: 
    (Left to right, most significant to least significant bit)
		msb                        lsb  
Input Pins:  	D7  D6  D5  D4  D3  D2  D1  D0	-- Data Bits
		C3  C2  C1  C0			-- Check Bits
Output Pins: 	Z7  Z6  Z5  Z4  Z3  Z2  Z1  Z0	-- Output Data Bits
Filename: sec
  3. Build a coin-operated vending machine, which accepts only quarters, dimes, and nickels. Coins are inserted until a total of 30 cents or more is deposited. Only one coin is deposited at a time. The output signal z1=1 should indicate that merchandise should be provided; z1=0 indicates no merchandise.
    Coincident with the last coin input, the (change) outputs are to be set. Assume the machine can give a dime (z2=1) and/or a nickel (z3=1).

  4. See CPU.pdf