ECS154A Homework #1

• Written homework due by 3:59PM on Thursday, July 3rd
• Logisim assignments due by 11:59PM on Thursday, July 3rd. Submit your assignment via Smartsite.
• Some terminology, in case it is not clear:
  • !A = NOT A = Abar
  • m1 = minterm 1, m5 = minterm 5, etc.
  • D1 = Don't Care at Truth Table location 1, D5 = Don't Care at 5, etc.

Assignment (Written):

1. Use algebraic minimization to prove that (A+B) * (A+!B) = A
   
2. Does A*!B + B*C + !A*!C = A*C + !B*!C + !A*B? (show how you made your decision!)
   
3. Does A*!C + !A*C + !C*!D = !A*C + !C*!D + A*!C*D? (show how you made your decision!)
   
4. Does A*C*D + A*B*!C + !A*!C*D + B*D = A*C*D + A*B*!C + !A*!C*D + !A*B*C + B*D? (show how you made your decision!)
   
5. f= A*!B*!E + !A*!B*!D*!E + A*B*D*E + !A*!B*C*!D + A*!B*C*E +!B*!C*D*!E + A*B*C*D*!E
   g= !B*C*!D + !B*!C*!D*!E + A*C*D*!E + A*!B*D*!E + A*C*D*E + !A*!B*!C*!E + A*B*!C*D*E
   Does f=g? (show how you made your decision!)
   
6. Draw the circuit (!X2*X3) + (!X3*X1). Now, draw the timing diagram for this circuit. Show the waveforms that can be observed on all wires in the circuit.
   
7. Find a minimum SOP expression for m0+m1+m2+m3+m4+m6+m7.
   
8. Find a minimum SOP expression for m1+m3+m4+m5+m6.
   
9. Find a minimum SOP expression for m0+m3+m4+m7+m9+m10+m13+m14.
   
10. Find a minimum SOP expression for A*C + A*!B + !A*B*C + !A*!B*!C
    
11. Find a minimum SOP expression for A*!B*!C + A*B*D + B*C*D + !A*!B*!C*!D
    
12. Find a minimum SOP expression for m1+m4+m7+D2+D5
    
13. Find a minimum SOP expression for m0+m2+m8+m9+m10+m15+D1+D3+D6+D7+D11
    
14. Find a minimum SOP expression for m0+m2+m5+m7+m8+m10+m13+m16+m18+m24+m26+D15+D22+D28
    
15. Show how the function f=m0+m2+m3+m4+m5+m7 can be implemented using a 3-8 binary decoder and an OR gate.
    
16. Consider the function f=!B*!C + A*B. Derive a circuit for f that uses a 2-1 multiplexor.
    
17. Determine the number of gates needed to implement an n-bit carry-lookahead adder, assuming no fan-in constraints. Use AND, OR, and XOR gates with any number of inputs.
18. What is the critical delay path in this multiplier? How many gates does the signal go through along this path?
    
    

Assignment (Logisim):

1. Design and implement the simplest circuit that has 3 inputs (A,B,C) and produces an output value of 1 whenever two or more of the input variables have the value 1. The output is to be 0 at all other times.
   
2. Design and implement a circuit that determines how many bits in a 5-bit unsigned number are 1.
   
3. Design and implement a BCD to 7-segment display code converter. Here is a link to the truth table and layout of the display. You can find an interactive example here
4. Design a 4-bit ALU using Logisim. Each bit cell should be able to do ADD, SUB, AND, NOT and OR. In addition, the adder should use Carry-Lookahead to improve performance. Your 4-bit ALU should employ group carry lookahead, with group size of 4 and ripple carry between groups. (In other words, correctly generate the carry out of the first group). You are to assume that all arithmetic operations are on 2's complement numbers. The NOT function should occur on the A inputs.
   The selector/control bits: AND=10, OR=01, NOT=00, ADD/SUB=11 Use the following naming convention:

    (Left to right, most significant to least significant bit)
   		msb     lsb 
   Input Pins:	B3 B2 B1 B0  -- B operand
   		A3 A2 A1 A0  -- A operand
                         S1 S0  -- The selector lines (desired operation) 
                           CIN  -- The Carry into the bottom cell
   Output Pins:	C3 C2 C1 C0  -- Result
   Filename: alu