ECS154A Homework #3

• Lab assignment due Sunday, May 22, 11:59 PM.
• Written homework due by 4:30 PM on Friday, May 20th.

LAB Assignment:

• Design a 6-bit CPU. Details here
  (If above link does not work, try this one

WRITTEN Assignment:

1. What is the difference between a subroutine and an interrupt-service routine? List at least 5 things that have to be changed in a processor in order to support interrupts.
   
   
2. Consider a 64-bit microprocessor, with a 32 bit external data bus, driven by a 1 GHZ input clock. Assume that this microprocessor has a bus cycle whose minimum duration equals 90 input clock cycles. What is the maximum data transfer rate that this microprocessor can sustain? To increase its performance, would it be better to make its external data bus 64 bits or to double the external clock frequency supplied to the microprocessor? State any assumptions you make, and explain.
   
   
3. Assume that in the Daisy-chained arrangement we discussed in class the processor keeps asserting BusGrant (BG) as long as BusRequest (BR) is asserted. When device i is requesting the bus, it becomes the bus master only when it receives a low-to-high transition on its BusGrant (BGi) input.
   
   
   a. Assume that devices are allowed to assert the BusRequest signal at any time. Give a sequence of events to show that the system can enter a deadlock situation, in which one or more devices are requesting the bus, the bus is free, and no device can become the bus master.
   
   
   
   b. Suggest a rule for the devices to observe in order to prevent this deadlock situation from occuring.
   
   
   
4. How would the timing in an asynchronous bus be affected if the distance between the processor and the I/O device is increased? How can this increased distance be accomodated in the case of a synchronous bus?
   
   
5. Draw and explain a timing diagram for a PCI write operation (similar to figure 3.23)
   
   
6. Here is a string of hex address references given as byte addresses:
   
   4,3,5,8,1A,17,14,1,9,11,23,3A,5,19,1,9
   
   
   a. Assuming a direct mapped cache with 16 one-byte blocks that is initially empty, label each reference in the list as a hit or miss and show the final contents of the cache tag array. Compute the hit rate for this example.
   
   
   b. Show the hits and misses and final cache contents for a direct mapped cache with four-byte blocks (lines) and a *total* size of 16 bytes. Compute the hit rate for this example.
   
   
   c. Show the hits and misses and final cache contents for a two-way set associative cache with one-byte blocks (lines) and a *total* size of 16 bytes. Assume LRU replacement. Compute the hit rate for this example.
   
   
   d. Show the hits and misses and final cache contents for a fully associative cache with one-byte blocks (lines) and a *total* size of 16 bytes. Assume LRU replacement. Compute the hit rate for this example.
   
   
   e. Show the hits and misses and final cache contents for a fully associative cache with four-byte blocks (lines) and a *total* size of 16 bytes. Assume LRU replacement. Compute the hit rate for this example.
   
   
7. A set associative cache consists of 64 lines divided into 4-line sets. (In other words, it is 4-way set associative). Each line is 4 bytes long. Main memory contains 4K blocks of 128 words each, and a word consists of 4 bytes. Show the format of main memory addresses.
   
   
8. Problem 4.7 from the book.
   
   
9. Consider a memory system that uses a 32-bit address and is byte addressable, and a cache that uses 64 byte lines.
   
   Assume a direct-mapped cache with a tag field in the address of 20 bits. Show the address format and determine the following parameters: number of lines in the cache, the size of the cache, and the size of the tag.
   
   Assume a fully-associative cache. Now how big is the tag?
   
   Assume a 4-way set associative cache with a tag field in the address of 9 bits. Show the address format and determine the following parameters: number of lines in the cache, size of the cache, number of lines per set, number of sets in the cache, and the size of the tag.
   
   
10. Design an 8-bit byte-addressable memory of total capacity 8192 bits using SRAM chips of size 64x1 bit. Give the array configuration of the chips on the memory board showing all required input and output signals for assigning this memory to the lowest address space.