ECS154A Homework #5

• Lab assignment due Monday, June 7th, 11:59 PM.
• Written homework due by 4:30 PM on Wednesday, June 2nd.

LAB Assignment:

• See lab5.html NOTE: Ignore this link until the TA's post to the newsgroup that it is correct!

WRITTEN Assignment:

1. Here is a string of hex address references given as byte addresses:
   
   4,3,5,8,19,17,14,1,9,11,23,36,5,19,1,9
   
   Assuming a direct mapped cache with 16 one-byte blocks that is initially empty, label each reference in the list as a hit or miss and show the final contents of the cache tag array. Compute the hit rate for this example.
   
   
2. Using the reference string from (1), show the hits and misses and final cache contents for a direct mapped cache with four-byte blocks (lines) and a *total* size of 16 bytes. Compute the hit rate for this example.
   
   
3. Using the reference string from (1), show the hits and misses and final cache contents for a two-way set associative cache with one-byte blocks (lines) and a *total* size of 16 bytes. Assume LRU replacement. Compute the hit rate for this example.
   
   
4. Using the reference string from (1), show the hits and misses and final cache contents for a fully associative cache with one-byte blocks (lines) and a *total* size of 16 bytes. Assume LRU replacement. Compute the hit rate for this example.
   
   
5. Using the reference string from (1), show the hits and misses and final cache contents for a fully associative cache with four-byte blocks (lines) and a *total* size of 16 bytes. Assume LRU replacement. Compute the hit rate for this example.
   
   
6. Design an 8-bit byte-addressable memory of total capacity 4096 bits using SRAM chips of size 64x1 bit. Give the array configuration of the chips on the memory board showing all required input and output signals for assigning this memory to the lowest address space.
   
   
7. A set associative cache consists of 64 lines divided into 4-line sets. (In other words, it is 4-way set associative). Each line is 4 bytes long. Main memory contains 4K blocks of 128 words each, and a word consists of 4 bytes. Show the format of main memory addresses.
   
   
8. Problem 4.7 from the book.
   
   
9. Consider a memory system that uses a 32-bit address and is byte addressable, and a cache that uses 64 byte lines.
   
   Assume a direct-mapped cache with a tag field in the address of 20 bits. Show the address format and determine the following parameters: number of lines in the cache, the size of the cache, and the size of the tag.
   
   Assume a fully-associative cache. Now how big is the tag?
   
   Assume a 4-way set associative cache with a tag field in the address of 9 bits. Show the address format and determine the following parameters: number of lines in the cache, size of the cache, number of lines per set, number of sets in the cache, and the size of the tag.
   
   
10. Problem 4.15 from the book. Use Tc = 40 ns, Tm = 920 ns, Cc = .005 cents/bit, Cm = .0006 cents/bit.