ECS154A Homework #3

• Lab assignment due Monday, November 16th, 11:59 PM.
• Written homework due by 4:30 PM on Monday, November 16th.

LAB Assignment:

• See lab4.html (NOTE 11/6/09 - this lab is not quite ready yet. We will let you know when it is.)

  WRITTEN Assignment:

  1. How do subroutine and an interrupt-service routines differ? List at least 5 things that have to be changed in the hardware of a processor in order to support interrupts.
     
     
  2. Assume you have a 64-bit microprocessor, with a 32 bit external data bus, driven by a 3.0 GHZ input clock. This microprocessor has a bus cycle whose minimum duration equals 125 input clock cycles. What is the maximum data transfer rate that this microprocessor can sustain? To increase its performance, would it be better to make its external data bus 64 bits or to double the external clock frequency supplied to the microprocessor? State any assumptions you make, and explain.
     
     
  3. Assume that in the Daisy-chained arrangement we discussed in class the processor keeps asserting BusGrant (BG) as long as BusRequest (BR) is asserted. When device i is requesting the bus, it becomes the bus master only when it receives a low-to-high transition on its BusGrant (BGi) input.
     
     
     a. Assume that devices are allowed to assert the BusRequest signal at any time. Give a sequence of events to show that the system can enter a deadlock situation, in which one or more devices are requesting the bus, the bus is free, and no device can become the bus master.
     
     
     
     b. Suggest a rule for the devices to observe in order to prevent this deadlock situation from occuring.
     
     
     
  4. How would the timing in an asynchronous bus be affected if the distance between the processor and the I/O device is increased? How can this increased distance be accomodated in the case of a synchronous bus?
     
     
  5. Draw and explain a timing diagram for a PCI write operation (similar to figure 3.23)