ECS154A Homework #3

• Lab assignment due Monday, November 19th, 11:59 PM.
• Written homework due by 4:30 PM on Tuesday, November 20th.

LAB Assignment:

• Design a 4-bit CPU. Details here

WRITTEN Assignment:

1. How do subroutines and interrupt-service routines differ? List at least 5 things that have to be changed in the hardware of a processor in order to support interrupts.
   
   
2. Consider a 16-bit embedded microprocessor, with an 8 bit external data bus, driven by a 1.5 GHZ input clock. Assume that this microprocessor has a bus cycle whose minimum duration equals 140 input clock cycles. What is the maximum data transfer rate that this microprocessor can sustain? To increase its performance, would it be better to make its external data bus 16 bits or to double the external clock frequency supplied to the microprocessor? State any assumptions you make, and explain.
   
   
3. Assume that in the Daisy-chained arrangement we discussed in class the processor keeps asserting BusGrant (BG) as long as BusRequest (BR) is asserted. When device i is requesting the bus, it becomes the bus master only when it receives a low-to-high transition on its BusGrant (BGi) input.
   
   a. Assume that devices are allowed to assert the BusRequest signal at any time. Give a sequence of events to show that the system can enter a deadlock situation, in which one or more devices are requesting the bus, the bus is free, and no device can become the bus master.
   
   
   b. Suggest a rule for the devices to observe in order to prevent this deadlock situation from occuring.
   
   
   
4. How would the timing in an asynchronous bus be affected if the distance between the processor and the I/O device is increased? How can this increased distance be accomodated in the case of a synchronous bus?
   
   
5. Draw and explain a timing diagram for a PCI write operation (similar to figure 3.23)
   
   
6. Here is a string of hex address references given as byte addresses:
   
   3,1,2,A,B,2B,17,18,3,9,22,23,24,5,19,1,9
   
   
   a. Assuming a direct mapped cache with 16 one-byte blocks that is initially empty, label each reference in the list as a hit or miss and show the final contents of the cache tag array. Compute the hit rate for this example.
   
   
   b. Show the hits and misses and final cache contents for a direct mapped cache with four-byte blocks (lines) and a *total* size of 16 bytes. Compute the hit rate for this example.
   
   
   c. Show the hits and misses and final cache contents for a two-way set associative cache with one-byte blocks (lines) and a *total* size of 16 bytes. Assume LRU replacement. Compute the hit rate for this example.
   
   
   d. Show the hits and misses and final cache contents for a two-way set associative cache with two-byte blocks (lines) and a *total* size of 16 bytes. Assume LRU replacement. Compute the hit rate for this example.
   
   
   e. Show the hits and misses and final cache contents for a fully associative cache with one-byte blocks (lines) and a *total* size of 16 bytes. Assume LRU replacement. Compute the hit rate for this example.
   
   
   f. Show the hits and misses and final cache contents for a fully associative cache with four-byte blocks (lines) and a *total* size of 16 bytes. Assume LRU replacement. Compute the hit rate for this example.
   
   
7. Consider a memory system that uses a 32-bit address and is byte addressable, and a cache that uses 128 byte lines.
   
   Assume a direct-mapped cache with a tag field in the address of 19 bits. Show the address format and determine the following parameters: number of lines in the cache, the size of the cache, and the size of the tag.
   
   Assume a fully-associative cache. Now how big is the tag?
   
   Assume a 4-way set associative cache with a tag field in the address of 11 bits. Show the address format and determine the following parameters: number of lines in the cache, size of the cache, number of lines per set, number of sets in the cache, and the size of the tag.
   
   
8. Consider a machine with a byte addressable main memory of 2^16 (65536) bytes, which has a direct-mapped cache with 32 lines. Lines are 8 bytes long.
   
   a. How is the 16-bit memory address partitioned by the cache? (In other words, how big is the tag field, the entry into the line, etc.)?
   
   b. Into what line would bytes with each of the following addresses be stored?
   0x111B
   0xC334
   0xD01D
   0xAAAA
   
   c. Suppose the byte with address 0x1A1A is stored in the cache. What are the addresses of the other bytes stored along with it?
   
   d. How many total bytes of memory can be stored in the cache?
   
   e. Why is the tag also stored in the cache?